Product Manager - Silicon Strategy & Security (Founders Office)
Ixana
Location: Bengaluru
Team: Founders Office – Product Strategy
Type: Full‑time
Level: PM I/ PM II
Why this role
Own the strategy and roadmap for our chip/SoC/IP line, leading special projects directly overseen by founders. You’ll blend silicon know‑how with product judgment to design features, processes, and supply‑chain controls that deter cloning, over‑build, and counterfeits—while shipping things customers love.
What you’ll do
Product strategy & roadmap
Define product vision and north‑star metrics (e.g., security‑feature attach rate, counterfeit incidence, secured revenue).
Build the 12–18‑month roadmap balancing perf/power/area with security, yield, and cost.
Author crisp PRDs/MRDs; run prioritization and quarterly planning with design, verification, firmware, test, ops, and GTM.
IP‑protection strategy
Drive silicon/firmware features: unique device IDs (eFuse/OTP), PUF/silicon fingerprinting, secure boot & attestation, debug/JTAG lockdown, logic/bitstream obfuscation, watermarking, anti‑tamper packaging.
Define factory personalization & licensing/activation (key injection, challenge–response) and track‑and‑trace with Ops.
Partner with Legal/IP on patents, licensing terms, and enforcement levers; maintain a competitive dossier on clone vectors.
Execution & customer impact
Run cross‑functional sprints from concept → tape‑in/tape‑out → GA; manage EAPs/betas with lead customers.
Instrument feature adoption and security outcomes; publish dashboards and post‑launch learnings.
Enable Sales/FAE with positioning, pricing/packaging (tiered security SKUs), and reference enablement flows.
What success looks like (30/60/90)
30 days: Ramp on portfolio; map attack surfaces; align on success metrics.
60 days: Executive‑reviewed IP strategy and roadmap with cost/performance trade‑offs.
90 days: Pilot security stack locked (e.g., UID/PUF + secure boot + JTAG lock), with EAP customers in flight.
What you’ll bring
Must‑have
MBA from an IIM (or equivalent Tier‑1).
2+ years hands‑on chip/VLSI/EDA experience (Analog/RTL/SoC/DV/DFT/firmware for silicon).
Ability to write PRDs, define metrics, and drive trade‑offs across security vs. PPA vs. cost.
Working grasp of hardware‑security building blocks (UID/OTP, PUF basics, secure boot, debug‑port security).
Strong cross‑functional leadership and crisp communication.
Nice‑to‑have
Prior PM/TPM experience in semiconductors/EDA/embedded security.
Exposure to reliability/DFR, yield/debug flows, or failure‑analysis labs.
Patents/publications; comfort with SQL/analytics for usage telemetry; familiarity with Jira/Confluence/Git.
How we work
High‑ownership culture in the Founders Office; you’ll work directly with founders/senior leadership on strategic bets.
Pragmatic agility: data‑driven decisions, short feedback loops with customers, and “secure‑by‑design” as a default.
Compensation & benefits
Competitive CTC with performance bonus and equity (ESOPs), comprehensive health cover, flexible/hybrid work, learning budget, and conference sponsorships.
Hiring process
Recruiter screen (15 min)
Product deep‑dive (problem framing, PRD exercise)
Security & silicon systems round (with Design/DFT/FW leads)
Cross‑functional loop (Ops/Legal/GTM)
Founder conversation & offer